Optimization Challenges in Transistor Sizing

Chandu Visweswariah
IBM Watson Research Center

The first half of this presentation will describe the application of
state-of-the-art nonlinear optimization techniques in a production
transistor sizing tool geared towards custom circuits. Special
techniques are employed to ensure efficient convergence. In the second
part, some of the deficiencies of current nonlinear optimization methods
will be pointed out, along with enumeration of interesting problems that
could be solved if the deficiencies are overcome.

Speaker bio
Presentation (PDF File)

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