Parallel Hardware Architectures for the Computation of the Tate Pairing

Luca Breveglieri
Politecnico di Milano
Dept. of Electronic Eng. and Information Sciences

Identity-based cryptography uses pairing functions, which are
sophisticated bilinear maps
defined on elliptic curves. Computing pairings efficiently in
software is presently a relevant
research topic. Since such functions are very complex and slow in
software, dedicated hardware
(HW) implementations are worthy of being studied, but presently only
somewhat preliminary research
is available. This talk affords the problem of designing parallel
dedicated HW architectures,
i.e. co-processors, for the Tate pairing. Such architectures can be
dedicated or programmed
on parallel hardware platforms, of which nowadays several models are
proposed and in part are
available. Formal scheduling methodologies are applied to carry out
an extensive exploration
of the architectural solution space, and to evaluate the obtained
structures by means of different
figures of merit such as computation time, circuit area and
combinations thereof. Comparisons
with the (few) existing proposals are carried out, showing that a
large space exists for the efficient
parallel HW computation of pairings.

Audio (MP3 File, Podcast Ready) Presentation (PDF File)

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