Applications of Robust Optimization in Integrated Circuit Design

Michael Orshansky
University of Texas at Austin

Robust optimization techniques have become increasingly accepted in the electronic design automation (EDA) community. I describe our work that has used advances in robust optimization to deal both with variability in parameter realizations and epistemic uncertainty in modeling of circuit behavior.

Nanometer scale semiconductor devices are characterized by the increasing unpredictability in their physical properties. Variability strongly impacts chip leakage power because of its exponential dependence on the highly varying transistor parameters leading to substantial parametric yield losses. I first introduce an optimization strategy in which fast run-time is achieved by casting the statistical power minimization algorithm as a second-order conic problem and solving it using efficient interior-point methods. Parametric yield loss can be effectively reduced by both design-time optimization strategies and by adjusting circuit behavior to the empirical realizations of variable parameters. The two levels of tuning operate within a single variability budget, and because their effectiveness depends on the magnitude and the spatial structure of variability their joint co-optimization is required. I describe an optimization algorithm for such co-optimization and link it to the control and measurement overhead via the formal notions of measurement and control complexity.

Another application of robust optimization I describe deals with epistemic uncertainty in modeling of circuit behavior. A major challenge in optimization of analog circuits is the inaccuracy resulting from fitting the complex behavior of scaled transistors to a restricted class of functions, e.g. posynomials. We advance a novel optimization strategy that circumvents these problems in the following manner: by explicitly handling the error of the model in the course of optimization, we find a potentially suboptimal, but feasible solution. This solution subsequently guides a range-refinement process of our transistor models, allowing us to obtain far more accurate circuit models. The key contribution is in using the available oracle (SPICE simulations) to identify solutions that are feasible with respect to the accurate behavior rather than the fitted model. The key innovation is the explicit link between the fitting error statistics and the rate of the error uncertainty set increase, which we use in a robust optimization formulation to find feasible solutions.

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