A variety of underlying mechanisms are known to cause variations in nanometer-scale digital circuits, and their impact on circuit performance parameters can be significant. These variations may arise due to probabilistic shifts in process parameter values, or from environmental variations due to thermal and supply voltage changes, or due to aging and reliability effects. Under this backdrop, one can see that some circuit optimizations may be formulated as robust optimization problems. This talk will overview problem statements and solutions in the area of predicting on-chip variations and overcoming their effects to build circuits that are resilient to perturbations.
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