The uncertainty imposed by nanoscale fabrication techniques causes significant parametric variations in the fabricated VLSI chips. Controlling design parameters such as gate size, gate placement, wire routes etc for optimization of the parametric yields has become a popular topic of research. This talk focuses on some of our recent work on how to exploit the convexity property exhibited by some VLSI circuit optimization problems for optimizing the parametric yields. Furthermore, this talk describes techniques that allow balancing of the pre and post fabrication methods for countering the impact of fabrication randomness. Post fabrication correction based schemes allow the chip to be designed for the nominal case while correcting any violations post fabrication when the uncertainty manifests itself. Pre fabrication approaches focus on designing the chip with sufficient guardbands that ensure correct operation despite manufacturing uncertainty.
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