Real-time decoding for fault-tolerant quantum computers
Michael Beverland
IBM
Real-time decoding for fault tolerance is a central challenge as we move beyond NISQ. The decoding timescale is set by the QEC cycle time of the hardware, which is microseconds for superconducting platforms. Meeting this constraint likely requires specialized classical hardware such as FPGAs or ASICs, whose high degree of parallelism changes the relative performance of decoding algorithms, for example allowing Gaussian elimination to run in linear parallel time on FPGAs rather than cubic time on CPUs, and therefore motivates hardware-aware redesign rather than direct porting of CPU-based methods. In this talk, I discuss recent progress toward real-time decoding under these constraints, and argue that message-passing decoders, particularly the Relay-BP algorithm, offer a promising route to real-time decoding. Relay-BP improves on the convergence of standard belief propagation while retaining a lightweight, highly parallel structure suitable for FPGA implementation, and significantly outperforms alternative decoders for quantum LDPC codes. Beyond average decoding speed, I address the backlog problem that arises from variable decoding latency. I present conditions on decoder latency distributions under which fast average-case decoding and sufficiently light latency tails allow decoding to keep pace with syndrome generation, ensuring bounded computational slowdown in large-scale fault-tolerant computations.
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