From NISQ to Fault Tolerance: Architecting the Accelerated Quantum Supercomputer
Adam Holmes
NVIDIA
Applied Research
Scaling from today’s noisy quantum devices to fault-tolerant quantum computers is no longer primarily a qubit fabrication problem, it is a systems integration problem. As quantum processors grow, the dominant bottlenecks shift to real-time calibration, quantum error correction, and low-latency classical orchestration, all of which demand tight coupling between QPUs, GPUs, CPUs, and networking. In this talk, we present an emerging blueprint for an accelerated quantum supercomputer, where ultra-low-latency quantum–classical interconnects enable real-time feedback, GPUs and AI drive decoding and calibration at scale, and unified programming models allow hybrid workflows to span hardware seamlessly. We discuss how accelerated emulation, AI-assisted control and decoding, and heterogeneous system design are redefining what it means to build a scalable quantum computer, and how these capabilities collectively bridge the gap from NISQ-era demonstrations to truly fault-tolerant, scientifically useful quantum systems.
Back to Bridging the Gap Between NISQ and FTQC