This presentation will focus on the challenge of optimizing digital
integrated circuits in the face of inevitable and increasing process
variations. The talk will consist of three main parts. In the first part,
a quick tutorial introduction to statistical timing analysis will be
provided. Statistical timing is an efficient and accurate way of taking
process variations into account during integrated circuit design. In
the second part, recent work in continuous transistor sizing of custom
digital macros by exploiting statistical timing will be described. In the
final section, open challenges in discrete circuit optimization during
physical synthesis will be formulated.
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